AMD details Fusion innovations at ISSCC

Forthcoming chip with four CPU and one GPU cores will also be power-efficient.

AMD is to disclose details of its first Fusion processor today at the International Solid State Circuits Conference (ISSCC) in San Francisco, with an emphasis on design features that will boost the energy efficiency of the forthcoming chip.

Fusion aims to combine standard CPU and graphics processor (GPU) technology into a single chip capable of handling complex calculations such as those required for 3D graphics as well as traditional applications, producing what AMD calls an accelerated processing unit (APU).

Codenamed Llano, the first Fusion APU will sample in the first half of this year and be commercially available in 2011, AMD said. This is set to have four CPU cores plus a GPU supporting Microsoft's DirectX 11 APIs, and will also be the firm's first 32nm processor.

"The reason for Fusion is that we ran out of gas on single-core chips, and we realised there is a lot of value if we can exploit heterogeneous computing, which means a lot more than just integrating a GPU," said AMD senior fellow Sam Naffziger.

However, the chief innovations AMD will discuss at ISSCC will be the power management features in Llano, which will be manufactured using a High-K metal gate process.

Among these is the ability to completely disconnect any of the processor cores from the power supply if they are not being used, according to Naffziger.

"If only graphics type calculations are being performed, we can disconnect all of the CPUs and just leave the GPU running, for example," he said.

Completely disconnecting a core greatly reduces current leakage, and this switching is fast enough that cores can power up and down between user keystrokes, Naffziger claimed.

Llano will also feature a digital power management module capable of accurately tracking power consumption in each core, enabling the clock speed to be maximised while staying within thermal constraints.

"This digital approach is a lot better than today's analogue designs whereby you just have to assume the worst case and then budget conservatively," Naffziger explained.

The third innovation involves optimisation of the clock signal distribution around the chip to cut the power required. Traditionally, brute force has been used to push the signal to all corners of the chip without significant delays (known as clock skew), with the result that 20 to 30 percent of a CPU's power budget can be accounted for by the clock alone.

With Llano, AMD's chip designers have carefully relocated various components of the chip to prune away whole areas of the clock grid and reduce the number of clock buffers by 50 percent, according to Naffziger.

"What we did is analyse the grid and push [the clock] out to just a limited set of areas. This enabled a cascade of reductions in power consumption," he said.

The result is that Llano will be efficient enough to serve as a mobile processor, according to Naffziger, although he declined to detail whether this meant Llano will be used in laptops or some other device format.

In architecture, the CPU cores of Llano are effectively tweaked versions of those in AMD's Opteron processors, while the GPU is based on the technology in high-end ATI graphics accelerators.

"The underlying architecture [of the CPUs] is the same as our x86 platform, but we've added some non-trivial tweaks to squeeze out even more performance," said Naffziger.

He contrasted AMD's Fusion architecture with Intel's recently introduced Westmere chips, which also integrate graphics functions inside the processor chip package but on a second, separate piece of silicon to the actual CPU cores.

"We are not using a low-end GPU, we're taking our leading state-of-the-art GPU and integrating it on the same chip so it shares the high-bandwidth DDR3 memory and features a high-speed communications channel between all the cores," he said.