Intel's new Tremont architecture targets low-power, compact devices

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Intel's new Tremont architecture targets low-power, compact devices

Intel has introduced its new Tremont CPU architecture that promises significant performance gains for IoT devices and other kinds of products with requirements for low-power and small form factors.

The company said Tremont, which was announced at the Linley Fall Processor conference on Thursday, provides a significant increase in instructions per cycle over the previous generation architecture for Atom processors, Goldmont Plus.

The chipmaker expects Tremont to work well for a wide variety of purposes, including client computing, data center, 5G networking and IoT. One of the first confirmed devices using the new Tremont architecture is Microsoft's dual-screen Surface Neo, which will run on Intel's Lakefield hybrid CPU architecture that included integrated Tremont cores.

"Tremont is Intel's most advanced low-power x86 architecture to date. We focused on a range of modern, complex workloads, while considering networking, client, browser and battery so that we could raise performance efficiently across the board," Stephen Robinson, Intel's chief architect for Tremont, said in a statement. "It is a world-class CPU architecture designed for enhanced processing power in compact, low-power packages."

Intel said Tremont will feature advancements in instruction set architecture, microarchitecture, security and power management. According to a presentation by Robinson at the Linley conference, it will include new instruction sets and technologies, like Intel Trusted Execution Technology and Intel Boot Guard as well as Intel Total Memory Encryption for improved security at the memory level.

The Microsoft Surface Neo's use of Tremont will serve as a preview for how Intel is working to shake up the way it develops processors. For instance, the Lakefield processor in the Surface Neo will integrate Tremont cores and other silicon IP thanks to the company's new 3D chip packaging technology, Foveros, which allows for the integration of high-performance, low-power and high-density chiplets.

This article originally appeared at crn.com

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